emitter coupled logic technical , ECL (abbreviation)

Emitter coupled logic is very fast but uses a lot of power.

A differential amplifier is used as the input stage emitter coupled logic gates and as switch.

The hardware implementation of the HEP PEM was emitter coupled logic.

Furthermore, the input and output impedances of Emitter Coupled Logic were comparable to the characteristic impedance of ribbon cable.

The Modular One was a 16-bit computer built with Emitter Coupled Logic (ECL) and was competitive with other first generation minicomputers.

High Speed Bipolar Logic From the earliest days there was an alternative to TTL, called emitter coupled logic, ECL.

Once all 9 signals have been scanned via the hunt algorithm, the strongest one is selected, amplified, and sent off-chip as a digital positive emitter coupled logic (PECL) output signal.

FASTBUS uses the Emitter coupled logic (ECL) electrical standard, which allows higher speed than TTL and generates less switching noise.

Explain the operation of Emitter Coupled Logic (ECL) logic circuits and be able to plot the transfer characteristic and calculate the risetime for an ECL inverter.

The Elxsi processor was an Emitter Coupled Logic (ECL) design that featured a 50 nanosecond clock, a 25 nanosecond backpanel bus, IEEE floating point arithmetic and a 64-bit architecture.

When the new processor technology finally arrives next year, it will have been a decade since I.B.M. began developing the new generation of mainframes based on a widely used technology for making chips, known as emitter coupled logic, that is at the heart of its new processor.

Half size Emitter Coupled Logic (ECL) Clock Oscillators 10 MHz to 140 MHz All dimensions are in mm OSO-HSH-B00C OSO-HSH-B00D Above Specifications when Pin 8 is grounded, spiral denotePin 1 connection.