microinstruction

A field from the microinstruction is used for jumps, or other logic.

For example, a single typical microinstruction might specify the following operations:

A counter is used for the typical case, that the next microinstruction is the one to execute.

This is because the machine will work faster if the execution of the next microinstruction is delayed by one cycle.

It has a six-stage microinstruction pipeline and 64-entry fully associative translation look-aside buffer.

This is very similar to the way CPUs with microcode execute one microinstruction per cycle.

Usually the addresses are generated by some combination of a counter, a field from a microinstruction, and some subset of the instruction register.

Microinstruction Memory Array (160 x 45 bits)

The Geometry Engine uses a 195-bit microinstruction, which is compressed in order to reduce size and bandwidth usage in return for slightly less performance.

Each microinstruction in a microprogram provides the bits which control the functional elements that internally compose a CPU.

The CPU had a microinstruction cycle period of 170 ns (5.88 MHz).

The translation tables were cached in the CPU resulting, in most cases, in an overhead of only one microinstruction when performing address translation.

Each element is differentiated by the "micro" prefix to avoid confusion: microinstruction, microassembler, microprogrammer, microarchitecture, etc.

To simultaneously control all processor's features in one cycle, the microinstruction is often wider than 50 bits, e.g., 128 bits on a 360/85 with an emulator feature.

Consequently each horizontal microinstruction is wider (contains more bits) and occupies more storage space than a vertical microinstruction.

It contained a 16-bit 29116 microprocessor clocked at 10 MHz with a 10 KB memory containing 2,048 40-bit words of microinstruction memory.

For each tick it is common to find that only some portions of the CPU are used, with the remaining groups of bits in the microinstruction being no-ops.

This refers primarily to whether each microinstruction directly controls CPU elements (horizontal microcode), or requires subsequent decoding by combinatorial logic before doing so (vertical microcode).

Alternatively we can start at the level of registers and transfers between registers, and describe our architecture in terms of these primitives; a microinstruction set would be an example here.

The MIB (microinstruction bus) carried microinstructions control signals and addresses from the control store to the I/E and F chips.

The term pipeline refers to the fact that each step is carrying a single microinstruction (like a drop of water), and each step is linked to another step (analogy; similar to water pipes).

Very often the execution of the next microinstruction is dependent on the result of the current microinstruction, which will not be stable until the end of the current microcycle.

In vertical microcode, each microinstruction is encoded-that is, the bit fields may pass through intermediate combinatory logic which in turn generates the actual control signals for internal CPU elements (ALU, registers, etc.).

The IBM ACS-1 design of 1967 allocated a "skip" bit in its instruction formats, and the CDC Flexible Processor in 1976 allocated three conditional execution bits in its microinstruction formats.

The only restriction this placed upon the microcode was that if the p-code required more than one microinstruction, then the first microinstruction couldn't have any flow control specified (as it would be filled in with a "goto ).