The architecture uses a set of seven registers to manipulate and interpret fetched data and instructions.

All instruction fetches come from the code segment in the CS register.

For example, an operation on a character string could be done as a single machine instruction, thus avoiding multiple instruction fetches.

Thus we may be able to initiate an instruction fetch from store and increment the program counter in one micro-instruction.

The ROB works by storing instructions in their original fetched order.

Some of these stages include instruction fetch, instruction decode, execute, and write back.

Once again assuming a uniform distribution of branch instruction placements, 0.5, 1.5, and 3.5 instructions fetched are discarded.

The instruction queue is filled with the instructions fetched from the memory.

Only the instruction fetch feature is removed, and placed in the ACU.

Instructions were fetched in 72-bit word pairs, reducing effective instruction fetch time to 1.0 s.